In a semiconductor test process, a conductivity test is sometimes performed to detect a defective product by bringing probes having conductivity (conductive probes) into contact with a semiconductor wafer before dicing (WLT: Wafer Level Test). When this WLT is performed, to transfer a signal for a test generated and sent by a testing device (tester) to the semiconductor wafer, a probe card including a large number of probes is used. In the WLT, the probes are individually brought into contact with each of dies on the semiconductor wafer while the dies are scanned by the probe card. However, because several hundreds to several ten thousands dies are formed on the semiconductor wafer, it takes considerable time to test one semiconductor wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the WLT, recently, a method called FWLT (Full Waver Level Test) is also used in which several hundreds to several ten thousands probes are collectively brought into contact with all or at least a quarter to a half of dies on a semiconductor wafer. In this method, to accurately bring the probes into contact with the semiconductor wafer, there are known technologies for maintaining positional accuracy of tips of probes by accurately keeping the parallelism or the flatness of a probe card with respect to a predetermined reference surface and for highly accurately aligning a semiconductor wafer.
In testing a semiconductor wafer using a probe card, it is necessary to obtain stable contact resistance between probes of the probe card and electrode pads provided in the semiconductor wafer. Such contact resistance is related to a load exerted on the probes. It is known that the load exerted on the probes increases in proportion to a stroke of the probes. Therefore, to obtain stable contact resistance between the probes and the electrode pads in the test, it is important to accurately control the stroke of the probes within a predetermined range.    Patent Document 1: Japanese Patent Application Laid-Open No. 2005-164600    Patent Document 2: Japanese Patent Application Laid-Open-No. 2005-164601    Patent Document 3: Japanese Patent No. 3386077